In semiconductor device manufacturing, forming features on the substrate is frequently required wherein the shape and dimension of the feature depends on the type of device that is to be manufactured. One standard technique for forming features involves patterning a material layer using, for instance a combination of lithography and etching. A drawback with this technique is however that the etchants may react with the material that is patterned in such a way that the electronic properties of the material are adversely affected at the edges of the features (i.e. the boundary surfaces of the features which are formed during the etching). This drawback may be more pronounced as device dimensions, and thus the dimensions of the features, are reduced.